Conventional tools exist for generating a high-level model that integrates co-processing with soft/hard processing and hardware co-simulation capability seamlessly into a simulation and modeling environment. Some tools address co-processing and hardware co-simulation by using memory-mapped input/outputs (I/Os). Memory-mapped I/Os provide a homogeneous interface to access input and output ports and shared memory blocks of a design by abstracting inputs/outputs with address spaces and memory read/write operations. In hardware co-simulation, a memory map interface couples a design to a co-simulation engine. In a co-processing arrangement, a memory map interface couples the design to a shared or dedicated bus of a processor. Each I/O port of the design is mapped to a specific region of a common address space. A port is associated with a memory location such that a write operation pushes a new value onto an input port and a read operation reads the current value from an output port. A shared memory block is mapped to a range of memory locations to enable burst read and write operations.
However, there are many challenges in providing a flexible mapping between a software simulation and an arbitrary design, and in providing a transparent integration between the co-processing/co-simulation machinery and varying I/O interfaces of different designs.